Device Family: Stratix® V

Type: Answers, Errata

Area: EMIF, Intellectual Property



Failure May Occur For LRDIMM Designs Simulated with NCSIM and Targeting Stratix V Devices

Description

This problem affects DDR3 products.

For DDR3 LRDIMM designs targeting Stratix V devices, LRDIMM example designs simulated with NCSIM 12.20-s003 may experience failure during compilation of the LRDIMM buffer simulation model. The failure occurs because NCSIM does not yet support the SystemVerilog alias keyword, which is used to connect two bi-directional buses.

Workaround/Fix

The workaround for this issue is to connect the bidirectional DQ/DQS ports of the LRDIMM model using Verilog tran primitives.

For example, open the file alt_mem_if_common_ddr_mem_model_ac_parity_ddr3_lrdimm_mem_if_dqsn_en.sv

in a text editor, and search for the following lines:

alias w_ranka_mem_dqs = lrdimm_mdqs_p[MEM_DQS_A_U: MEM_DQS_A_L]; alias w_ranka_mem_dqs_n = lrdimm_mdqs_n[MEM_DQS_A_U: MEM_DQS_A_L]; alias w_ranka_mem_dqs_n = lrdimm_mdqs_n[MEM_DQS_A_U: MEM_DQS_A_L];

Replace the above lines with the following statement:

genvar k; generate for (k = MEM_DQ_A_L; k <= MEM_DQ_A_U; k = k + 1) begin : gen_ranka_mem_dq tran inst_tran (w_ranka_mem_dq[k-MEM_DQ_A_L], lrdimm_mdq[k]); end for (k = MEM_DQS_A_L; k <= MEM_DQS_A_U; k = k + 1) begin : gen_ranka_mem_dqs tran inst_tran_p (w_ranka_mem_dqs[k-MEM_DQS_A_L], lrdimm_mdqs_p[k]); tran inst_tran_n (w_ranka_mem_dqs_n[k-MEM_DQS_A_L], lrdimm_mdqs_n[k]); end endgenerate

This issue will be fixed in a future release.