Type: Answers, Errata
Area: Intellectual Property

Last Modified: November 19, 2013
Version Found: v11.0
Version Fixed: v13.1

RapidIO IP Core Qsys Design Example Simulation Warning


When you simulate the RapidIO Qsys design example, warning messages display. These messages complain of a missing rio_sys_onchip_memory2_0.hex file.


This issue has no impact on simulation. You can ignore these warning messages.

To avoid this issue, copy the rio_sys_onchip_memory2_0.hex file from the rio_sys/simulation/submodules directory to the current working directory.

This issue is fixed in version 13.1 of the RapidIO MegaCore function.