Article ID: 000075486 Content Type: Troubleshooting Last Reviewed: 06/02/2021

Why does the HDMI Intel® FPGA IP encounter audio failure in HDMI audio packet layout 1 configuration?

Environment

  • Quartus® II Subscription Edition
  • HDMI Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Due to a problem starting in version 14.0 of the Intel® Quartus® software, the HDMI Intel® FPGA IP may encounter audio failure in HDMI audio packet layout 1 configuration.

    This is due to the HDMI Intel® FPGA Source IP is expecting continuous audio channel allocation only while CTA-861 specification allows for discontinuous audio channel allocation.

    • For instance in 4 channel audio mode,  audio data packet sent through audio channel 1, 2, 3 and 5 (skipping audio channel 4) is a valid configuration but the HDMI Intel® FPGA Source IP will interpret it as missing audio data packet scenario 

     

     

    Resolution

    This problem is fixed starting with the Intel® Quartus® Prime Pro Edition software version 21.2.

    Related Products

    This article applies to 5 products

    Intel® Cyclone® 10 GX FPGA
    Intel® Stratix® 10 GX FPGA
    Intel® Arria® 10 FPGAs and SoC FPGAs
    Arria® V FPGAs and SoC FPGAs
    Stratix® V FPGAs