Device Family: Intel® Arria® 10, Intel® Stratix® 10

Intel Software: Quartus Prime Pro

Type: Answers

Area: Intellectual Property


Last Modified: January 13, 2021
Version Found: v20.1
Bug ID: 1508722677
IP: cpri

Why does the eCPRI Intel® FPGA IP assert mac_source_sop and mac_source_valid after the mac_source_ready is de-asserted?

Description

Due to the ready latency of the eCPRI Intel® FPGA IP's mac_source_ready is 3 clock cycles, you may observe the mac_source_sop and mac_source_valid are asserted after the mac_source_ready is de-asserted.

Workaround/Fix

This is an expected behavior of the IP.

This information will be updated into a future version of the eCPRI Intel® FPGA IP User Guide.