Due to the ready latency of the eCPRI Intel® FPGA IP's mac_source_ready is 3 clock cycles, you may observe the mac_source_sop and mac_source_valid are asserted after the mac_source_ready is de-asserted.
Device Family: Intel® Arria® 10, Intel® Stratix® 10
Intel Software: Quartus Prime Pro
Area: Intellectual Property
Last Modified: January 13, 2021
Version Found: v20.1
Bug ID: 1508722677