Article ID: 000075584 Content Type: Troubleshooting Last Reviewed: 08/16/2023

The Intel® Stratix® 10 E-Tile Triple-Speed Ethernet Intel® FPGA IP Design Example is not functional in hardware.

Environment

  • Intel® Quartus® Prime Pro Edition
  • Triple-Speed Ethernet Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    The Intel® Stratix® 10  E-Tile Triple-Speed Ethernet Intel® FPGA IP Design Example available in the Intel® Quartus® Prime Pro Edition Software versions 21.1 supports simulation using the provided testbench in both Synopsys* VCS* and Mentor* Modelsim.

    Hardware test is not supported in version 21.1 of the Intel® Quartus® Prime Software.

    The timing analyzer may report timing violations when compiling the example design in version 21.1 of the Intel® Quartus® Prime Software.

    Resolution

    To work around this problem in Intel® Quartus® Prime Pro Edition Software version 21.1, install the patch below:

    Download the version 21.1 patch 0.15 for Linux (.run)

    Download the version 21.1 patch 0.15 for Windows* (.exe)

    Download the Readme for version 21.1 patch 0.15 (.txt)

    This problem is fixed starting with the Intel® Quartus® Prime Pro Software version 21.3.

    A patch for version 21.2 of the  Intel® Quartus® Prime Pro Software is available from the link below:

    Why does the Intel® Stratix® 10 E-Tile Triple-Speed Ethernet Intel® FPGA IP Design Example generation fail?

    Related Products

    This article applies to 3 products

    Intel® Stratix® 10 TX FPGA
    Intel® Stratix® 10 DX FPGA
    Intel® Stratix® 10 MX FPGA