Device Family: Intel® Stratix® 10 DX

Intel Software: Quartus Prime Pro

Type: Answers

Area: Intellectual Property

Last Modified: June 19, 2020
Version Found: v20.1
Bug ID: 1507957102
IP: Avalon-MM Stratix 10 Hard IP for PCI Express

Why does the Intel® P-Tile Avalon® Memory Mapped IP for PCI Express* Design Example error during simulation if the debug toolkit is enabled?


Due to a problem in the Intel® Quartus® Prime Pro Edition software version 20.1 or earlier, Intel® P-Tile Avalon® Memory Mapped Hard IP for PCI Express* Example Design with enabling debug toolkit feature reports error during simulation.

Error-[CFCILFBI] Cannot find cell in liblist  ./../..//../../../pcie_ed/sim//../../ip/pcie_ed/pcie_ed_dut/sim//../intel_pcie_ptile_ast_200/sim/ptile_debug_toolkit/, 285


To work around this problem, disable the debug toolkit feature when generating the simulation environment.

The Intel® FPGA P-Tile Avalon® Memory Mapped IP for PCI Express* User Guide is scheduled to be updated to detail this restriction.