Device Family: Intel® Agilex™ F-Series, Intel® Stratix® 10 DX

Intel Software: Quartus Prime Pro

Type: Answers

Area: Intellectual Property


Last Modified: June 19, 2020
Version Found: v20.1
Bug ID: 1507965203
IP: Avalon-MM Stratix 10 Hard IP for PCI Express

Why does the Intel® P-Tile Avalon® Memory Mapped IP for PCI Express* Gen4x4 Root Port Example Design error during compilation?

Description

Due to a problem in the Intel® Quartus® Prime Pro Edition software version 20.1 or earlier, the Intel® P-Tile Avalon® Memory Mapped IP for PCI Express* Gen4x4 Root Port Example Design reports error during compilation.

Error(21410): Verilog HDL error at s10_rp_avmm_master_hwtcl.v(130): event control statement inside subprogram is not supported for synthesis

Workaround/Fix

To work around this, it is necessary to generate the simulation and synthesis file separately and re-compile the examaple design.

This problem is scheduled to be addressed in a future release of the Intel® Quartus® Prime Pro Edition Software.