Device Family: Intel® Stratix® 10 DX, Intel® Stratix® 10 GX, Intel® Stratix® 10 MX, Intel® Stratix® 10 SX, Intel® Stratix® 10 TX

Intel Software: Quartus Prime Pro

Type: Errata

Area: Intellectual Property


Last Modified: June 19, 2020
Version Found: v19.4
Bug ID: 1507878462
IP: Avalon-ST Stratix 10 Hard IP for PCI Express, Avalon-MM Stratix 10 Hard IP for PCI Express

Why is the Slot Clock Configuration bit setting of the Avalon® -ST Intel® Stratix® 10 Hard IP for PCI Express* and Avalon® -MM Intel® Stratix® 10 Hard IP for PCI Express* is always 0 regardless of the setting in the IP Catalog ?

Description

Due to a problem with the Avalon® -ST Intel® Stratix® 10 Hard IP for PCI Express* and Avalon® -MM Intel® Stratix® 10 Hard IP for PCI Express* in Intel® Quartus® Prime Pro Edition version 19.4, the Slot Clock Configuration bit (bit 12) in the PCI Express Link Status register is always set to 0. This problem can be seen in both simulation and hardware. 

Workaround/Fix

There is no workaround. This problem will be fixed in a future version of the Intel® Quartus® Prime Pro Edition software.