Device Family: Intel® Agilex™ F-Series, Intel® Stratix® 10 DX

Intel Software: Quartus Prime Pro

Type: Answers

Area: Intellectual Property


Last Modified: October 12, 2020
Version Found: v20.2
Bug ID: 14012264636
IP: Avalon-MM Stratix 10 Hard IP for PCI Express

Why is the Intel® FPGA P-Tile Avalon® Memory-mapped IP for PCI Express* GUI showing incorrect data bus width and clock frequency?

Description

Due to a problem in the Intel® FPGA P-Tile Avalon® Memory-mapped IP for PCI Express* for the Intel® Quartus® Prime Pro Edition software version 20.2, the GUI will show incorrect data bus width and clock frequency. 

Workaround/Fix

The Intel® FPGA P-Tile Avalon® Memory-mapped IP for PCI Express* User Guide, Table PHY Clock and Application Clock Frequencies, lists the correct values of data widths and application clock frequency (p_app_clk) for the Intel® FPGA P-Tile Avalon® Memory-mapped IP for PCI Express*.

https://www.intel.com/content/www/us/en/programmable/documentation/aib1557867923977.html#rsc1567029023459

 

This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition software.