Device Family: Intel® Arria® 10, Intel® Stratix® 10

Intel Software: Quartus Prime Pro, Quartus Prime Standard

Type: Answers

Area: Intellectual Property


Last Modified: September 09, 2020
Version Found: v19.3
Bug ID: 1508187436
IP: 25G Ethernet

Why does the 25G Ethernet Intel® FPGA IP fail to achieve 100% throughput?

Description

Due to problem in the 25G Ethernet Intel® FPGA IP core, for Intel® Quartus® Prime<Pro/Standard> version 20.2 and earlier, you may see the IP fail to achieve 100% throughput.

This is because the IP does not compensate for the data rate loss due to RSFEC Alignment Marker Insertion on the TX data path. The 25G Ethernet Intel® FPGA IP Core is not adhering to section 108.5.2.2 "rate compensation for codeword markers in the transmit direction" of the IEEE 802.3 spec. As a result, the IP is unable to achieve throughput higher than 99.995%.

Workaround/Fix

No workaround to this problem exists.

This problem is scheduled to be fixed in future release of the Intel® Quartus® Prime <Pro/Standard> Edition software.