UG-20160 | 2020.06.29 and earlier versions indicate that the file <your_ip>.regmap will be created when generating the Stratix® 10 E-Tile Hard IP for Ethernet Intel® FPGA IP and E-Tile CPRI PHY IP Core. This is incorrect. The file <your_ip>.regmap is not generated.
Device Family: Intel® Stratix® 10 DX, Intel® Stratix® 10 MX, Intel® Stratix® 10 TX
Area: Documentation, Intellectual Property
Last Modified: September 23, 2020
Version Found: v19.4
Version Fixed: v20.2
Bug ID: 1508021320
Document Version Found: January 31, 2020