Device Family: Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10

Intel Software: Quartus Prime Pro

Type: Answers, Errata

Area: Intellectual Property


Last Modified: February 03, 2020
Version Found: v19.3
Version Fixed: v19.4
Bug ID: 1507396739
IP: Low Latency Ethernet 10G MAC

Why does the Low Latency Ethernet 10G MAC Intel® FPGA IP generated design example simulation fail?

Description

Due to a problem with the Intel® Quartus® Prime Pro software version 19.3, the Low Latency 10G MAC Intel® FPGA IP generated design example may encounter the above problem. This is because the simulation model outputs an "X" (undefined) instead of valid data,  this causes the block lock signal to de-assert and the simulation then stops. 

Workaround/Fix

This problem has been fixed starting in the Intel® Quartus® Prime Pro Edition software version 19.4.