Device Family: Intel® Stratix® 10 GX, Intel® Stratix® 10 MX, Intel® Stratix® 10 SX, Intel® Stratix® 10 TX

Intel Software: Quartus Prime Pro

Type: Answers, Errata

Area: Intellectual Property


Last Modified: December 02, 2020
Version Found: v19.2
Bug ID: 1508145708, 1508506571
IP: Avalon-MM Stratix 10 Hard IP for PCI Express

Why does the host system receive corrupted data without LCRC error or Completion Time Out error on a PCIe* Gen 3 x16 link that uses the Intel® Stratix® 10 Hard IP for PCI Express* in the Intel® Stratix® 10 L-Tile and H-Tile devices ?

Description

The Tx FIFO almost full threshold setting of the Intel® Stratix® 10 Hard IP for PCIe* Gen 3 x16 variant are marginal, you may see corrupted data without LCRC error or Completion Time Out error that doesn't result a link recovery on a PCIe* Gen 3 x16 link that uses the Intel® Stratix® 10 Hard IP for PCI Express in the Intel® Stratix® 10 L and H-Tile devices. The other IP variants like PCIe* Gen 3 x8 and Gen 3 x4 are not affected.

Workaround/Fix

There is no workaround to this problem. 

This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Edition software.