Device Family: Intel® Agilex™ F-Series, Intel® Stratix® 10

Type: Answers, Documentation, Errata

Area: Intellectual Property

Last Modified: October 07, 2020
Version Found: v20.2
Bug ID: 18013057286
Document ID: UG-20160
Document Version Found: July 13, 2020
IP: Transceiver PHY Reset Controller, ethernet, Stratix 10 Transceiver PHY Reset Controller, Transceiver Reconfiguration Controller

Why does the E-Tile Hard IP for Ethernet fail to achieve RX PCS alignment and successfully link up when dynamically reconfigured from 100GbE MAC + PCS with RS-REC variant to 100GbE MAC + PCS without RS-FEC?


Due to a mistake in the E-Tile Hard IP User Guide, a Reset Controller register required when switching from 100G MAC + PCS with RS-FEC to 100G MAC + PCS mode is not documented.

The E-Tile RS-FEC includes a port called rsfec_signal_ok. When performing dynamic reconfiguration from one mode to another the reset controller waits for this signal to assert as part of the reset sequence. However, in the non RS-FEC mode, this signal will not assert, this results in the channel getting stuck in reset when switching from 100G RS-FEC mode to non RS-FEC mode.

Bit[5] of the undocumented reset controller register at address 0x313 instructs the reset controller to ignore the rsfec_signal_ok port.


This undocumented E-Tile reset controller register is correctly used in the E-Tile 100G Ethernet Dynamic Reconfiguration Design Example.

  • When switching from 100G MAC + PCS with RS-FEC to 100G MAC + PCS non RS-FEC mode set Bit[5] of register 0x313
  • When switching from 100G MAC + PCS non RS-FEC to 100G MAC + PCS with RS-FEC clear Bit[5] of register 0x313

This missing information will be added to a future release of the E-Tile Hard IP for Ethernet user guide.