Device Family: Intel® Stratix® 10

Intel Software: Quartus Prime Pro

Type: Errata

Area: Intellectual Property

Last Modified: July 15, 2020
Version Found: v18.1
Bug ID: 1507076280
IP: S10 PCIE DMA Controller, Avalon-MM Stratix 10 Hard IP for PCI Express

Why does the PCIe* DMA Controller Intel® Stratix® 10 FPGA IP send two continuous MSI interrupts for the DMA operation?


Due a problem in the PCIe* DMA Controller Intel® Stratix® 10 FPGA IP, the DMA controller will send out two continuous MSI interrupts, one if for the DMA Read MSI vector and the other is for the DMA Write MSI vector.

When either a DMA Read or DMA Write operation completes, if the driver programs the “Write Data Mover Interrupt Control Register”(MSI Address and Vector For DMA Write) and the “Read Data Mover interrupt control register” (MSI Address and Vector For DMA Read), both interrupts will be sent.


To work around this problem, please use the alternative method to send the MSI interrupts by programing the last descriptor of the DMA read or DMA write operation as the MSI Address and MSI Vector.