Device Family: Intel® Agilex™ F-Series, Intel® Stratix® 10 DX

Intel Software: Quartus Prime Pro

Type: Answers

Area: Intellectual Property

Last Modified: July 21, 2020
Version Found: v19.3
Version Fixed: v20.1
Bug ID: 14010307524
IP: Avalon-ST Stratix 10 Hard IP for PCI Express

Why does my Intel® P-Tile Avalon®-ST for PCI Express* IP RX interface behave differently depending on the reset condition?


The Intel® P-Tile Avalon®-ST for PCI Express* IP implements a deskew module in the FPGA fabric to realign receive side packets coming from Embedded Multi-die Interconnect Bridge (EMIB) interface. The deskew module has a reset problem that could cause misalignment on the Avalon-ST RX interface.


This problem is fixed in the Intel® Quartus® Prime Pro Edition software version 20.1.