Device Family: Intel® Stratix® 10

Type: Answers

Area: Intellectual Property


Last Modified: October 21, 2020
Version Found: v20.3
Bug ID: 1508300397

Why does simulation of the eSRAM Intel® FPGA IP targeting the Intel® Stratix® 10 using Mentor* ModelSim* show incorrect read data?

Description

When simulating the eSRAM Intel® FPGA IP targetting the Intel® Stratix® 10 devices with Mentor* ModelSim*, you may observe incorrect read data due to incorrect simulation options.

Workaround/Fix

To work around this problem, add the option below in the msim_setup.tcl file:
set USER_DEFINED_VERILOG_COMPILE_OPTIONS "+define+ESRAM_SIM"

This problem is due to be fixed in a future release of the Intel® Quartus® Prime software.