Due to a problem in the Intel® Quartus® Prime Pro Edition version 19.2 Software, the Intel® FPGA Triple-Speed Ethernet IP core Design Example MAC + 2xTBI PCS + E-tile PMA variant, when the "Enable E-tile transcevier dynamic reconfiguration" option is selected, Mentor* Modelsim simulation will run forever.
This is due to the Intel® Stratix® 10 E-tile Avalon Memory Map reconfig_clk and reconfig_reset ports not being properly connected in the design example Mentor* Modelsim simulation test bench file.