Device Family: Intel® Arria® 10, Arria® V, Intel® Cyclone® 10 GX, Cyclone® V, Intel® Stratix® 10, Stratix® V

Intel Software: Quartus Prime Pro, Quartus Prime Standard

Type: Answers, Errata

Area: Intellectual Property

Last Modified: July 20, 2020
Version Found: v14.0
Version Fixed: v20.1
Bug ID: 1507691362
IP: DisplayPort

Why does the DisplayPort Intel® FPGA IP fail to output video when Vtotal of Main Stream Attribute (MSA) field is greater than 13-bit width?


Due to a problem in version 14.0 and later of the Intel® Quartus® Prime software, the DisplayPort Intel® FPGA IP Pixel Clock Recovery Interface Hsync and Vsync signals stick low when the condition below is met:

  • Video resolution with Vtotal Main Stream Attribute (MSA) field exceeding 13-bit width or 8191 in decimal.


This problem is fixed starting from the Intel® Quartus® Prime Pro Edition version 20.1 Software onwards.