Device Family: Intel® Stratix® 10

Intel Software: Quartus Prime Pro

Type: Answers, Errata

Area: Intellectual Property


Last Modified: April 22, 2020
Version Found: v20.1
Bug ID: 1507840334
IP: 25G Ethernet

Why does the 25G Ethernet Intel® Stratix® 10 FPGA IP Design Example simulation run hang?

Description

Due to a problem in the Intel® Quartus® Prime Pro Edition version 20.1 Software, the design example generated by the 25G Ethernet Intel® Stratix® 10
FPGA IP with dynamic reconfiguration and PTP enabled, will hang when simulated with either Synopsys* VCS* simulator or Cadence* Xcelium*/NCSIM* simulator. 

Workaround/Fix

To avoid this problem, user is encounraged to use Mentor* Modelsim* simulator to simulate the design example.

This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition software.