Due to a problem with the simulation model of the Intel® FPGA Triple-Speed Ethernet IP core, both rx_clk and tx_clk output of the Intel® FPGA Triple-Speed Ethernet IP core stop after about 1.7 sec in the simulation.
This is due to the MSB of the internal 32-bits clock counter not toggled.
This problem can be seen in only simulation.
Device Family: Arria® V, Cyclone® V, Stratix® V
Intel Software: Quartus Prime Standard
Area: Intellectual Property
Last Modified: July 15, 2020
Version Found: v17.0
Bug ID: 22010710267
IP: Triple-Speed Ethernet