Device Family: Intel® Agilex™, Intel® Stratix® 10

Type: Answers

Area: Intellectual Property


Last Modified: September 09, 2020
Version Found: v19.3
Bug ID: 1507895122
IP: ethernet

Why does the CDR fail to lock in 25G mode when using the E-Tile Hard IP for Ethernet when the PHY reference frequency is set to 312.5MHz on Intel® Stratix® 10 and Intel® Agilex™ E-tile FPGAs?

Description

The E-tile PHY doesn't support reference clock frequency of 312.5MHz hence this frequency is not supported when using the E-Tile Hard IP for Ethernet in 25G mode.

Due to a mistake in both the user guide and the ip, this frequency is incorrectly provided as an option for this mode.

Workaround/Fix

No workaround to this problem exists, an alternative refclk frequency must be used for 25G E-Tile interfaces.

This mistake and detail will be updated in future releases of the E-Tile Hard IP for Ethernet GUI and the respective user guide.

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