Due to the reset staggering feature of the Intel® Stratix® 10 L-Tile transceivers and H-Tile transceivers, you may observe significant link up delay difference between Serial Lite III Streaming Intel® FPGA IP instances in simulation.
Device Family: Intel® Stratix® 10
Intel Software: Quartus Prime Pro
Area: Intellectual Property
Last Modified: April 08, 2020
Version Found: v18.1
Bug ID: 1507843925
IP: SerialLite III Streaming