Device Family: Intel® Agilex™ F-Series, Intel® Stratix® 10 DX

Type: Answers

Area: Intellectual Property


Last Modified: July 06, 2020
Version Found: v20.1
Version Fixed: v20.2
Bug ID: 14011186254
IP: Avalon-MM Stratix 10 Hard IP for PCI Express

When using the Intel® FPGA P-Tile Avalon® memory-mapped IP for PCI* Express, why is the "PCIe0 Link" tab in GUI missing?

Description

In v20.1 of the Intel® Quartus® Prime Pro Edition software, the Intel® FPGA P-Tile Avalon® memory-mapped IP for PCI* Express "PCIe0 Link" tab is missing from the IP GUI.

This problem prevents the user from enabling or disabling the "Slot Clock" reference clock from the connector.

Workaround/Fix

This problem has been fixed starting in v20.2 of the Intel® Quartus® Prime Pro Edition software.