When using the E-Tile Hard IP for Ethernet Intel® FPGA IP 10G/25G PTP variants , the o_sclk signal is an asynchronous pulse routed through clock network. Timing Analyzer incorrectly identifies the o_sclk signal as a clock source and reports it as an unconstrained clock.
Device Family: Intel® Agilex™ F-Series, Intel® Stratix® 10 DX, Intel® Stratix® 10 TX
Intel Software: Quartus Prime Pro
Type: Answers, Errata
Area: Intellectual Property
Last Modified: September 14, 2020
Version Found: v19.4
Bug ID: 18012564112