Device Family: Intel® Stratix® 10, Intel® Stratix® 10 DX, Intel® Stratix® 10 GX, Intel® Stratix® 10 MX, Intel® Stratix® 10 NX, Intel® Stratix® 10 PX, Intel® Stratix® 10 SX, Intel® Stratix® 10 TX

Intel Software: Quartus Prime Pro

Type: Answers, Documentation, How-To

Area: Intellectual Property


Last Modified: October 08, 2020
Version Found: v20.3
Version Fixed: v20.3
Bug ID: 16011850084
IP: Partial Reconfiguration

When using Intel® Stratix® 10 how do I recover from an error state after sending a corrupted partial reconfiguration bitstream?

Description

When the Intel® Stratix® 10 Partial Reconfiguration Controller Intel® FPGA IP detects a corrupted partial bitstream, it sets status[2..0] = 3'b100 = PR_ERROR is triggered. The avst_sink_ready signal is de-asserted and the Partial Reconfiguration Controller Intel® FPGA IP will not accept any further partial reconfiguration bitstream until the IP is reset using the reset port.

Before resetting the Partial Reconfiguration Controller Intel® FPGA IP it is necessary to ensure that the remaining partial bitstream is flushed from the Avalon® streaming pipeline, and only then assert the reset to the Partial Reconfiguration Controller Intel® FPGA IP.
 

Workaround/Fix

To work around this problem implement RTL to monitor the status[2..0] port and generate a dummy avst_sink_ready signal to the Intel® Stratix® 10 Partial Reconfiguration Controller Intel® FPGA IP Master when PR_ERROR is indicated and ensure avst_sink_valid has finished toggling. This will ensure the remaining partial reconfiguration bitstream is flushed from the Avalon® streaming pipeline, then apply the reset to the Intel® Stratix® 10 Partial Reconfiguration Controller Intel® FPGA IP.

Once completed it will be possible to start sending a new good partial reconfiguration bitstream to the Partial Reconfiguration Controller Intel® FPGA IP.