Device Family: Intel® Agilex™ F-Series, Intel® Stratix® 10 DX

Intel Software: Quartus Prime Pro

Type: Answers

Area: Intellectual Property


Last Modified: November 20, 2020
Version Found: v20.3
Bug ID: 14012971431, 14012971362
Document ID: UG-20237 | 2020.11.17
IP: Avalon-MM Stratix 10 Hard IP for PCI Express

What is the correct clock to use for the application clock domain when using the Intel® FPGA P-Tile Avalon® Memory-mapped IP for PCI Express*?

Description

The p<n>_app_clk (where n=1,2,3,4) is the correct clock to use as the application clock for the Intel® FPGA P-Tile Avalon® Memory-mapped IP for PCI Express*. The Intel® FPGA P-Tile Avalon® Memory-mapped IP for PCI Express* User Guide revision UG-20237 | 2020.11.17, incorrectly refers to coreclkout_hip as the application clock. Similarly the Intel® FPGA P-Tile Avalon® Memory-mapped IP for PCI Express* currently generates a top level coreclkout_hip port which should not be used as the application clock.

Workaround/Fix

The Intel® FPGA P-Tile Avalon® Memory-mapped IP for PCI Express* User Guide and the IP top level RTL are scheduled to be updated in the future release of the document and the IP.