Device Family: Intel® Agilex™, Intel® Stratix® 10

Type: Answers

Area: Intellectual Property


Last Modified: December 14, 2020
Version Found: v18.1
Bug ID: 22011735522
IP: JTAG to Avalon Master Bridge

Is there a known problem with the master_reset output of the JTAG to Avalon Master Bridge component when using Intel® Stratix® 10 or Intel® Agilex™ devices?

Description

Yes, due to a known problem in the Intel® Quartus® Prime Pro Edition software version 20.4 and earlier, the master_reset output of the JTAG to Avalon Master Bridge component may be unstable and create spurious reset assertions when used in Intel® Stratix® 10 or Intel® Agilex™ devices. 

This is because the JTAG logic that produces this asynchronous reset output is not reset after configuration and since the initial state of the register is unknown, the behavior of this reset output is unpredictable after device configuration.

Workaround/Fix

Do not use the master_reset output of the JTAG to Avalon Master Bridge IP as a reset source to any logic when using the Intel® Stratix® 10 or the Intel® Agilex™ devices.

This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition software.