Device Family: Intel® Agilex™, Intel® Agilex™ F-Series, Intel® Stratix® 10 MX, Intel® Stratix® 10 TX

Intel Software: Quartus Prime Pro

Type: Answers

Area: Intellectual Property


Last Modified: June 17, 2020
Version Found: v19.2
Version Fixed: v20.1
Bug ID: 1507475443
IP: jesd

Is the supported range for Control Bits (CS) in the JESD204C Intel® FPGA IP correct?

Description

Due to a known problem in Intel® Quartus® Prime Pro software version 19.4 and earlier, the JESD204C Intel® FPGA IP has a Control Bits (CS) range of 0 - 31. However the supported range is 0 - 3. 

Workaround/Fix

Select Control Bits (CS) within 0 - 3 range when using the JESD204C Intel® FPGA IP. This problem is fixed starting with the Intel® Quartus® Prime Pro Edition software version 20.1.