Device Family: Intel® Agilex™ F-Series, Intel® Stratix® 10 DX, Intel® Stratix® 10 MX, Intel® Stratix® 10 TX

Intel Software: Quartus Prime Pro

Type: Answers, Errata

Area: Intellectual Property


Last Modified: October 07, 2020
Version Found: v19.4
Version Fixed: v20.2
Bug ID: 18010781193
Document ID: UG-20160 | 2020.03.09
Document Version Found: March 09, 2020
IP: ethernet, Low Latency 100G Ethernet

Is the Ready Latency parameter supported when using the E-Tile Hard IP for Ethernet Intel® FPGA IP Core in 100G mode with PTP enabled?

Description

Due to a bug in the Intel® Quartus® Prime Pro Edition software the E-Tile Hard IP for Ethernet Intel® FPGA IP Core in 100G mode incorrectly allows the Ready Latency parameter to be selected when PTP mode is enabled.
The Ready Latency parameter is not supported in the E-Tile Hard IP for Ethernet Intel® FPGA IP Core in 100G mode if PTP is enabled?

When using the E-Tile Hard IP for Ethernet Intel® FPGA IP Core in 100G mode with PTP enabled, the Ready Latency is fixed at zero.

Workaround/Fix

No workaround for this problem exists.

This problem has been fixed starting with the v20.2 release of the Intel® Quartus® Prime Pro Edition software by removing the Ready Latency parameter from the IP GUI when PTP mode is selected.