Device Family: Intel® Stratix® 10 GX, Intel® Stratix® 10 MX, Intel® Stratix® 10 SX, Intel® Stratix® 10 TX

Type: Answers, Documentation

Area: Documentation, Intellectual Property


Last Modified: September 23, 2020
Version Found: v19.4
Version Fixed: v20.1
Bug ID: 1508184113
Document ID: UG-20109
Document Version Found: April 13, 2020
Document Version Fixed: July 29, 2020
IP: 25G Ethernet

How do I use the channel_reset port in the 25G Ethernet Intel® Stratix® 10 FPGA IP?

Description

Due to a mistake in the UG-20109 | 2020.04.13, there is no description of channel_reset port for 25G Ethernet Intel® Stratix® 10 FPGA IP. The channel_reset port is a reset input that is only present if the Enable 10G/25G Dynamic Rate Switching option is checked. Before initiating reconfiguration between speeds, assert this signal to hold the TX/RX data paths in reset. 

Workaround/Fix

This missing information has been added in UG-20109 | 2020.07.29.