Device Family: Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10

Type: Answers

Area: Intellectual Property


Version Found: v18.1
Bug ID: 1508306011
IP: SDI II

How do I set different video patterns in the SDI II Intel® FPGA IP design example testbench?

Description

By default in testbench tb_top.v, TEST_RECONFIG_SEQ is set to "half". The video pattern will be reconfigured in sequence of 12GA-->6GB-->3GA-->HS-->SD.

This shows a good example of reconfiguration, but gives too short a time to detail transmit video data pattern for mode.

Workaround/Fix

Modify the TEST_RECONFIG_SEQ parameter to set different video patterns in simulation.

For example, change it to "12GA" to run simulation of 12G video bitstream.

This parameter supports multiple options, "full", ''half', "12GA".. etc.

Refer to tb_tasks.v for detailed parameter values.