Article ID: 000076247 Content Type: Product Information & Documentation Last Reviewed: 02/15/2023

How do I set different video patterns in the SDI II Intel® FPGA IP design example testbench?

Environment

  • Intel® Quartus® Prime Pro Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    By default in testbench tb_top.v, TEST_RECONFIG_SEQ is set to "half." The video pattern will be reconfigured in the sequence of 12GA-->6GB-->3GA-->HS-->SD.

    This shows an excellent example of reconfiguration but gives too short a time to detail transmits video data pattern for mode.

     

     

    Resolution

    Modify the TEST_RECONFIG_SEQ parameter to set different video patterns in the simulation.

    For example, change it to "12GA" to run a simulation of a 12G video bitstream.

    This parameter supports multiple options, "full", ''half', "12GA".. etc.

    Refer to tb_tasks.v for detailed parameter values. 

    Related Products

    This article applies to 3 products

    Intel® Cyclone® 10 GX FPGA
    Intel® Arria® 10 FPGAs and SoC FPGAs
    Intel® Stratix® 10 FPGAs and SoC FPGAs

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