Device Family: Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10
Intel Software: Quartus Prime
Type: Answers
Area: Intellectual Property
Due to restriction of the Triple-Speed Ethernet Intel® FPGA IP with option "LVDS" as "Transceiver type", IOPLLs can't be merged.
You may see this error in the Intel® Quartus® Prime software when you initiate multiple Triple-Speed Ethernet Intel® FPGA IP with option "LVDS" as "Transceiver type" in single I/O bank for the Intel® Arria® 10, Intel® Cyclone® 10 GX or Intel® Stratix® 10 L-Tile/H-Tile device.
To avoid this error, follow the steps below:
1, Generate the Triple-Speed Ethernet Intel® FPGA IP with option "None" as "Transceiver type".
2, Generate the LVDS SERDES Intel® FPGA IP with multiple channels.
3, Connect two IPs manually.
This problem will not be fixed in a future version of the Intel® Quartus® Prime software.