Device Family: Intel® Agilex™, Intel® Arria® 10, Intel® Cyclone® 10, Intel® Stratix® 10

Intel Software: Quartus Prime Pro

Type: Answers, How-To

Area: DSP, Intellectual Property


Last Modified: May 20, 2020
Version Found: v19.2
Version Fixed: v20.1
Bug ID: 1507660634
IP: FIR II

Error: VHDL error at auk_dspip_roundsat_hpfir.vhd(103): value "4294967295" is outside the target constraint range (-2147483848 to 2147483647)

Description

Due to a problem in the Intel® Quartus® Prime Pro Edition software version 19.2, the error above can be seen when the output width of the FIR II Intel® FPGA IP is greater than or equal to 32 bits in rounding mode.

Workaround/Fix

To work around this error in existing software, set the IP parameter "Output LSB Rounding" to "Truncation", or still use "Rounding", but ensure that the output width is smaller than 32 bits.

This problem has been fixed starting with the Intel® Quartus® Prime Pro Edition software version 20.1.