Device Family: Intel® Agilex™ F-Series, Intel® Stratix® 10 DX

Intel Software: Quartus Prime Pro

Type: Answers, Errata

Area: Intellectual Property


Last Modified: June 22, 2020
Version Found: v20.1
Version Fixed: v20.2
Bug ID: 14011160563, 14011160835
IP: Avalon-ST Stratix 10 Hard IP for PCI Express

Error: intel_pcie_ptile_ast_0.dummy_user_avmm_rst has an associatedClock of "p1_hip_reconfig_clk" which could not be found

Description

Due to a problem with the Intel® FPGA P-Tile Avalon® streaming IP for PCI* Express, and error of the form shown above will be seen if the option "Enable Completion Timeout Interface" is selected in the IP GUI. This is due to the completion timeout interface being incorrectly associated with the hip_reconfig_clk. This error prevents the IP from being generated.

Workaround/Fix

In v20.1 of the Intel® Quartus® Prime Pro Edition of software, no workaround to this problem exists, generate the IP with the option "Enable Completion Timeout Interface" disabled.

This problem has been fixed starting in v20.2 of the Intel® Quartus® Prime Pro Edition of software.