Is “s2f_cold_reset_reset_n” from Hard Processor System Intel® Stratix® 10 FPGA IP active low reset?

Due to a problem in the Intel® Quartus® Prime Pro Edition software version 20.1 and earlier versions, when you enable “Enable HPS-to-FPGA cold reset output” option in Hard Processor System Intel® Stratix® 10 FPGA IP, a signal “s2f_cold_reset_reset_n” is exported in the top level.

The reset is a not an active low reset, but an active high reset.