Device Family: Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10

Intel Software: Quartus Prime Pro

Type: Errata

Area: Intellectual Property


Last Modified: January 23, 2020
Version Found: v19.1
Version Fixed: v19.3
Bug ID: 1507279766
IP: Triple-Speed Ethernet

Why is the Control Status Register(CSR) latency inconsistent during back-to-back interleaved reads between TX and RX statistics counter in the Triple-Speed Ethernet Intel® FPGA IP operating in 10Mbps speed mode?

Description

Due to a problem in the Intel® Quartus® Prime Software version 19.1 and 19.2, inconsistent CSR latency will be observed during back-to-back interleaved reads between TX and RX statistics counters in the Triple-Speed Ethernet Intel® FPGA IP operating in 10Mbps speed mode.

Workaround/Fix

To work around this problem, add interval of more than 1300ns between any Tx path statistics counter read to Rx path statistics counter read.

 

This problem has been fixed starting in the Intel® Quartus® Prime Pro Software version 19.3.