The Link Equalization Request bit (bit 5 of the Link Status 2 register) is set during PCIe* Gen3 link equalization. Once set, this bit cannot be cleared by software. The autonomous equalization mechanism is not affected by this issue, but the software equalization mechanism may be impacted depending on the usage of the Link Equalization Request bit.
Device Family: Intel® Arria® 10
Type: Answers, Errata
Area: Intellectual Property
Last Modified: April 27, 2020
Version Found: v17.1
Bug ID: 2205877260, 1608834679
IP: Arria 10 Hard IP for PCI Express