Device Family: Intel® Stratix® 10

Intel Software: Quartus Prime Pro

Type: Answers, Errata

Area: Intellectual Property

Last Modified: November 06, 2019
Version Found: v19.1
Bug ID: 1409586034, 1409325971
IP: Avalon-MM Stratix 10 Hard IP for PCI Express, Avalon-ST Stratix 10 Hard IP for PCI Express

Why are Non-Fatal PCIe* errors logged in Advanced Error Reporting (AER) when using the Intel® FPGA P-Tile/H-Tile , Avalon® Streaming and Avalon® Memory Mapped IP for PCI Express*?


The Intel® P-Tile/H-Tile PCIe* Hard IP implements optional ARI capability when Multi-function or SR-IOV are enabled. ARI capability includes a field called next function number in order to help the BIOS to perform enumeration. When ARI is enabled and the number of Physical Functions (PFs) is less than 8 (P-Tile) or 4 (H-tile), the next function number incorrectly shows a value of PF+1. As a result, the Correctable Error Status register in the Advanced Error Reporting (AER) capability structure may report a non-fatal error because Root Port issues configuration request to nonexisting PFs.


For H-Tile/P-Tile, software can clear the correctable error status register of the AER capability structure when this issue is encountered.

For P-Tile, user logic can use the Configuration Intercept Interface (CII) to correctly advertise the ARI next function number when a Configuration Read is issued by the Root Port.