Device Family: Intel® Arria® 10, Arria® II, Arria® V, Intel® Cyclone® 10, Cyclone® IV, Cyclone® V, Intel® MAX® 10, Intel® Stratix® 10, Stratix® IV, Stratix® V

Intel Software: Quartus Prime

Type: Answers

Area: DSP


Last Modified: March 06, 2019
Version Found: v18.1
Bug ID: 1507219116
IP: LDPC

Why is there port width mismatch when I try to connect the Encoder output directly to the Decoder input of the Intel® LDPC IP core?

Description

The output of the Intel® LDPC IP core Encoder cannot be directly connected to the input LPDC IP core Decoder. The output data of Encoder will need to undergo log-likelihood ratio (LLR) and soft bits conversion prior to feeding into input of Decoder. User will need to create the conversion logic using soft logic.

Workaround/Fix

There is no workaround required.