Device Family: Intel® Stratix® 10 TX

Intel Software: Quartus Prime Pro

Type: Answers, Errata

Area: Intellectual Property


Last Modified: July 01, 2019
Version Found: v19.2
Bug ID: 1507271106, 1507271106
IP: JESD204B

Why is the tx_ready_err CSR register bit flagged after the JESD204C IP is reset in the Intel® Stratix® 10 devices?

Description

After the JESD204C IP link is up in the Intel®  Stratix® 10 devices, if there is a warm reset applied to the IP, an unexpected tx_ready_err CSR register bit may be flagged right after the IP is reset.

This is due to the transceiver getting reset and tx_ready being deasserted after the mgmt_clk (avs_clk domain) is out of reset.

Workaround/Fix

To work around this problem do either of the following:

1. Clear the error interrupt.

 2. To avoid the interrupt, prolong the mgmt_clk (avs clk domain) reset when there is an IP reset, to avoid errors being flagged during the reset period. 

This problem is scheduled to be fixed in future release of the Intel® Quartus®  Prime Pro Edition software.