Due to a problem with the Intel® Stratix® 10 CIC Intel® FPGA IP in Intel® Quartus® Prime Pro Edition version 18.1 software, you may observe the output of this IP stuck at 0 in simulation when the IP is configured with Decimator filter type and the "Enable variable rate change factor" feature is turned ON.
Device Family: Intel® Stratix® 10
Intel Software: Quartus Prime Pro
Type: Answers
Area: DSP
Last Modified: July 03, 2019
Version Found: v18.1
Bug ID: 1507173061
IP: CIC
Why is the output of Intel® Stratix® 10 CIC Intel® FPGA IP Core for Intel® Quartus® Prime Pro Edition version 18.1 software generated example design stuck at 0 in simulation?
Description
Workaround/Fix
To work around this problem, change the raw data input in cic_ii_0_example_design_tb_input.txt in test_data directory into the following format:
data1, factor1
data2, factor2
...
For example:
0,8
16,8
...
This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition software.