Article ID: 000080671 Content Type: Troubleshooting Last Reviewed: 05/09/2019

Why is the last output frame of the Intel® FFT IP core missing EOP?

Environment

  • Intel® Quartus® Prime Pro Edition
  • FFT Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem with the Intel® FFT IP core in Intel® Quartus® Prime Standard software version 18.1, you may observe that the last output frame of the FFT IP core is missing EOP when both the Input Order and Output Order are configured to Natural and there are intervals with sink_valid = 0 between input frames.

    Resolution

    Configure the Output Order in FFT IP to be Digit Reverse.

    This problem will be fixed in a future version of the Intel Quartus Prime Standard software.

    Related Products

    This article applies to 11 products

    Cyclone® IV FPGAs
    Stratix® V FPGAs
    Intel® Stratix® 10 FPGAs and SoC FPGAs
    Cyclone® V FPGAs and SoC FPGAs
    Intel® Cyclone® 10 FPGAs
    Intel® Arria® 10 FPGAs and SoC FPGAs
    Arria® V FPGAs and SoC FPGAs
    Stratix® IV FPGAs
    Arria® II GX FPGA
    Arria® II GZ FPGA
    Intel® MAX® 10 FPGAs