Device Family: Intel® Stratix® 10, Intel® Stratix® 10 DX, Intel® Stratix® 10 MX, Intel® Stratix® 10 TX

Type: Answers

Area: Intellectual Property


Last Modified: March 16, 2020
Version Found: v19.2
Version Fixed: v19.3
Bug ID: 1409620228

Why is the Avalon® memory mapped bus unresponsive when reading the Intel® Stratix® 10 E-Tile Hard IP for Ethernet TX MAC, RX MAC, and PHY registers when auto negotiation and link training are enabled and the link is down?

Description

When using the Intel® Stratix® 10 E-Tile Hard IP for Ethernet with auto negotiation and link training enabled in the Intel® Quartus® Prime Pro Edition Software version 19.2 or earlier, the Avalon® memory mapped registers will not be accessible if the transceiver link is not yet established. 

Workaround/Fix

To work around this problem in the Intel® Quartus® Prime Pro Edition Software version 19.2 or earlier, establish the link with the transceivers before reading the TX MAC, RX MAC and PHY registers.

This problem has been fixed starting in the Intel® Quartus® Prime Pro Edition Software 19.3.