Device Family: Intel® Stratix® 10 GX, Intel® Stratix® 10 MX, Intel® Stratix® 10 SX, Intel® Stratix® 10 TX

Type: Answers, Errata

Area: Intellectual Property

Last Modified: Mon Jan 28 2019 06:28:00 GMT-0800
Version Found: v18.1
Bug ID: 2205829838

Why is fcs_error asserted for good packets when using the H-tile Hard IP for Ethernet Intel® FPGA IP in 50GBASE-R2 MAC+PCS mode on Intel® Stratix® 10 devices?


When using the Intel® Stratix® 10 H-Tile Hard IP for Ethernet Intel® FPGA IP in 50GBASE-R2 MAC+PCS Mode, fcs_error will incorrectly assert for good packets after a short frame has been received with the following aligned traffic:

• Frame size = 4Bytes in Word1 (excludes preamble)

• Another packet ends in the previous cycle - Word0 (IPG < 8)

When the H-tile for Ethernet Intel® FPGA IP in 50GBASE-R2 MAC+PCS Mode receives a frame, it strips the FCS from the frame and places it in an FCS FIFO, then calculates the FCS. When the FCS logic has finished calculating an FCS, it pops the frame FCS from the FIFO and compares it to the calculated result.

Frames that are short enough to require the FCS logic to do 2 pops in a single cycle can cause problems with this logic. The FIFO might see more pushes than pops, causing an overflow. For 100G and 25G configurations of the IP, a filter for short packets is in place to prevent this, the 50G implementation does not have this filter.


This problem is considered unlikely to occur due to random packet transfers.

Intel® currently have no plans to fix this problem in any future release of the Intel® Quatus® Prime Pro Edition of software.