When using the Stratix® V Avalon®-ST Interface for PCIe* IP, you may observe the reset_status signal toggling after pin_perst is released and before ltssmstate signal reaches Polling.Active (0x2). You can safely ignore this behavior and sample reset_status signal until the ltssmstate signal is greater than Polling.Active (0x2).
Device Family: Stratix® V
Intel Software: Quartus II, Quartus Prime Standard
Type: Answers, Errata
Area: Intellectual Property
Last Modified: Thu Apr 11 2019 13:11:00 GMT-0700
Version Found: v15.1 Update 1
Bug ID: 2007806331