Device Family: Intel® Stratix® 10

Intel Software: Quartus Prime Pro

Type: Answers, Errata

Area: Intellectual Property


Last Modified: May 23, 2019
Version Found: v18.0
Bug ID: 2205894092

Why does the Low Latency 100G Ethernet Intel® Stratix® 10 FPGA IP core fail to simulate using Cadence* NCSim and Xcelium when the RS-FEC is enabled?

Description

Due to a problem with the Low Latency 100G Ethernet Intel® Stratix® 10 FPGA IP core in RS-FEC mode, simulation will fail in both Cadence* NCSim and Xcelium.

An Error similar to the one shown below will be seen:

ncsim: *F,NOSNAP: Snapshot 'basic_avl_tb_top' does not exist in the libraries.

Workaround/Fix

To work around this problem, please use Synopsys* VCSMX or disable the RS-FEC.

This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Software.