Due to a problem with the Low Latency 100G Ethernet Intel® Stratix® 10 FPGA IP core in RS-FEC mode, simulation will fail in both Cadence* NCSim and Xcelium.
An Error similar to the one shown below will be seen:
ncsim: *F,NOSNAP: Snapshot 'basic_avl_tb_top' does not exist in the libraries.