When using the Low Latency 100G Ethernet Intel® FPGA IP with RSFEC and/or KR mode enabled on Intel® Stratix® 10 FPGA, timing violations can be observed.
Device Family: Intel® Stratix® 10 GX, Intel® Stratix® 10 MX, Intel® Stratix® 10 SX, Intel® Stratix® 10 TX
Type: Answers, Errata
Area: Intellectual Property
Last Modified: Mon Jan 28 2019 06:48:00 GMT-0800
Version Found: v18.0
Bug ID: 2205966624
Why does the Low Latency 100G Ethernet Intel® FPGA IP fail timing on Intel® Stratix® 10 FPGA?
Description
Workaround/Fix
To work around these timing violations when using Intel® Quartus® Prime version 18.0 or 18.1:
a. Check the placement of the Low Latency 100G Ethernet Intel® FPGA IP using the Quartus Prime Chip Planner.
If any hard block in the core is in the way of the placement of the Intel® Stratix® 10 100G IP, it may create long routing and results in bad timing.
If this is the case, please choose different set of transceiver locations when possible.
b. Try seed sweeping to get a better timing result.
This problem is scheduled to be improved but not fixed in a future version of the Intel® Quartus® Prime software.