Device Family: Intel® Stratix® 10

Intel Software: Quartus Prime Pro

Type: Answers

Area: Intellectual Property


Last Modified: November 06, 2019
Version Found: v17.1
Bug ID: 2205693312
IP: Avalon-MM Stratix 10 Hard IP for PCI Express

Why does the Intel® Stratix® 10 PCIe* Avalon® -MM Hard IP fail to respond to inbound memory read TLPs with the Relaxed Ordering bit set?

Description

Due to a limitation of the Intel® Stratix® 10 PCIe* Avalon® -MM Bridge, inbound memory read TLPs with the Relaxed Ordering bit set will be dropped and no completion returned , which can cause system failure.

Workaround/Fix

To work around this problem, constrain the link partner to only send the Memory read TLPs without the Relaxed Ordering bit set to the Intel® Stratix® 10 PCIe* Avalon® -MM Hard IP.