Due to a limitation of the Intel® Stratix® 10 PCIe* Avalon® -MM Bridge, inbound memory read TLPs with the Relaxed Ordering bit set will be dropped and no completion returned , which can cause system failure.
Device Family: Intel® Stratix® 10
Intel Software: Quartus Prime Pro
Area: Intellectual Property
Last Modified: November 06, 2019
Version Found: v17.1
Bug ID: 2205693312
IP: Avalon-MM Stratix 10 Hard IP for PCI Express