Device Family: Intel® Stratix® 10

Intel Software: Quartus Prime Pro

Type: Answers

Area: Intellectual Property


Last Modified: October 09, 2019
Version Found: v18.1
Bug ID: 1507076574
IP: Avalon-MM Stratix 10 Hard IP for PCI Express

Why does the Intel® Stratix® 10 PCI Express* Avalon®-MM Hard IP with External descriptor controller example design hang when more than 8 descriptors are programmed?

Description

Due to incorrect address mapping of the router logic generated by the Intel® Quartus® Prime Pro Platform Designer tool , the Intel® Stratix® 10 PCIe* Avalon®-MM Hard IP with External descriptor controller example design will hang when more than 8 descriptors are programmed.

Workaround/Fix

 

To work around this problem, manually correct the RTL files generated by the Intel® Quartus® Prime Pro Platform Designer tool:

 

1.   Search *altera_merlin_router*.sv under project workspace and find files shown below:

../altera_merlin_router_xxx/sim/altera_merlin_router_xxx (simulation flow)

../altera_merlin_router_xxx/syn/altera_merlin_router_xxx (implementation flow) 

 

2.   Open each file to confirm if following lines exist, then modify them accordingly:

Original lines should be:       

        //-------------------------------------------------------       

        // Figure out the number of bits to mask off for each slave span       

        // during address decoding       

        //-------------------------------------------------------       

        localparam PAD0 = log2ceil(64'h2000 - 64'h0);       

        localparam PAD1 = log2ceil(64'h1000100 - 64'h1000000);       

        localparam PAD2 =log2ceil(64'h1002100 - 64'h1002000);

Change to:       

        //-------------------------------------------------------       

        // Figure out the number of bits to mask off for each slave span       

        // during address decoding       

        //-------------------------------------------------------       

        localparam PAD0 = log2ceil(64'h2000 - 64'h0);       

        localparam PAD1 = log2ceil(64'h1001000 - 64'h1000000);   

        localparam PAD2 = log2ceil(64'h1003000 - 64'h1002000);

 

3.     Run the simulation or compilation flow again.

 

This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition software.